A) Field of the Invention
This invention relates to a solid-state imaging device, more particularly to a solid-state imaging device having a CCD-type transfer channel.
B) Description of the Related Art
FIG. 9 is a block diagram showing a structure of a conventional four-phase drive (φ1-φ4) charge coupled device (CCD) type solid-state imaging device 52 according to the prior art.
The solid-state imaging device 52 has an image area 60a, a multiplicity of photodiodes 62 arranged in a tetragonal matrix, and a vertical charge coupled device (VCCD) 64 arranged in correspondence with each column of the photodiodes. The VCCD 64 has a multi-layered electrode structure as described later.
At one end of the image area 60a, a horizontal charge coupled device (HCCD) 60b is configured. The HCCD 60b also has a multi-layered electrode structure similar to the VCCD 64. Following the HCCD 60b, an output amplifier 55 consisted of a high-speed analogue amplifier is configured.
Signal charges stored in the photodiodes 62 are transferred to the VCCD 64 simultaneously, and thereafter the VCCD 64 transfers the signal charges in a vertical direction in order. The signal charges transferred by the VCCD 64 are transferred in a horizontal direction row by row by the HCCD 60b and are output to the later-described analogue signal processing circuit 53 (FIG. 11) after being amplified by the output amplifier 55.
The output amplifier 55 is formed, for example, by including a charge/voltage (Q/V) converter consisted of a floating diffusion amplifier (FDA) and a source follower circuit.
Generally, the HCCD 60b transfers the signal charges by using high-speed transfer pulse over 14 MHz or over, and so power consumption of the HCCD 60b is high. The power consumption of the HCCD 60b counts about 40% of a total power consumption of the solid-state imaging device 52. Moreover, power consumption of the output amplifier 55 also counts about 40% of the total power consumption of the solid-state imaging device 52. Therefore, in the solid-state imaging device 52 according to the prior art, sum of the power consumption of the HCCD 60b and the output amplifier 55 counts about 80% of the total power consumption.
FIG. 10 schematically shows a structure of a double-layered poly-silicon electrode that is an example of the multi-layered electrode structure according to the prior art.
The VCCD 64 is formed, for example, by including a vertical transfer channel 614 made of an n-type impurity doped region formed on a p-well 611b of a semiconductor substrate 611a, an oxide film 615a formed on the vertical transfer channel 614, a first layer poly-silicon electrode 616a formed on the oxide film 615a, an inter-layer insulating film 615b formed by oxidizing the first layer poly-silicon electrode 616a, and a second layer poly-silicon electrode 616b formed on the inter-layer insulating film 615b and overlapping edge portions of the first layer poly-silicon electrode 616a. 
In the multi-layered electrode structure wherein the first layer poly-silicon electrode 616a and the second layer poly-silicon electrode 616b are laminated with placing the inter-layer insulating film 615b therebetween, the inter-layer insulating film 615b is formed by oxidizing a surface of the first layer poly-silicon electrode 616a. At a time of the oxidation, a Si surface exposing under the oxide silicon layer is also slightly oxidized. A film thickness of the oxide film 615a under the second layer poly-silicon electrode 616b will be thinner than a film thickness of the oxide film 615a under the first layer poly-silicon electrode 616a, and therefore, difference in the film thickness will be occurred.
In order to reduce an effect of the film thickness difference at the largest extent, the film thickness of the oxide film 615a has to be thick in advance. By making the film thickness thick, drive voltage of the electrode will be high. This point is a common feature of forming an inter-layer insulating film between laminated electrodes like the double-layered poly-silicon electrode shown in the drawing, a triple-layered poly-silicon electrode or the likes.
FIG. 11 is a block diagram showing a structure of an imaging system of a digital camera using an analogue output solid-state imaging device.
In an imaging system of a digital camera using a conventional solid-state imaging device, for example, an analogue signal processing circuit 53, an analogue/digital converter (ADC) 54, a digital signal processing circuit 63, a system controlling unit 5 and a storage medium 6 are connected to a bus line 7.
A solid-state imaging device 52 is, for example, a CCD type solid-state imaging device shown in FIG. 9. The solid-state imaging device 52 is connected to the analogue signal processing circuit 53 and supplies signal charges to the analogue signal processing circuit 53.
The system controlling unit 5 controls operations of the analogue signal processing circuit 53, the ADC 54, the digital signal processing circuit 63, a DRAM 4, and the storage medium 6, all of which are connected to the bus line 7.
Signal charges read from the solid-state imaging device 52 at a high-speed is supplied to the analogue signal processing circuit 53. The analogue signal processing circuit 53 is consisted of, for example, a noise-eliminating unit made of a correlated double sampling circuit, a color signal processing circuit, etc.
The ADC 54 converts analogue voltage signals into digital signals row by row and outputs them to the digital signal processing circuit 63. The digital signal processing circuit 63 can stores the input digital signals into the DRAM 4 row by row. Also, the digital signal processing circuit 63 reads the digital signals stored in the DRAM 4 and executes various image signal processes such as JPEG compressing and decompressing, etc. Moreover, the digital signal processing circuit 63 outputs the image signal processed digital signals to a monitor and stores them into the storage medium 6.
In addition to the above-described CCD type solid-state imaging device, there is a so-called frame interline transfer (FIT)-CCD having a charge storage region formed at one end of an image area. In the FIT-CCD, charge signals are transferred vertically at a high-speed and stored temporarily into the charge storage region formed at one end of an image area before being transferred horizontally. The high-speed charge transfer of the vertical charge coupled devices (VCCD) in the FIT-CCD can reduce smear noise of a CCD image sensor.
As described in the above, about 80% of the total power consumption of the conventional CCD type solid-state imaging device 52 is used by the HCCD 60b and the output amplifier 55. For increasing the number of pixels, further high-speed driving of the HCCD 60b and the output amplifier 55 will be necessary, and the power consumption will become higher.
In order to reduce the power consumption due to the high-speed driving, there is a CCD type solid-state imaging device having two HCCDs for doubling a transfer rate at the same transfer clock frequency.
Also, the above-described FIT-CCD used a multi-layered poly-silicon electrode, it was difficult to drive a VCCD at a high-speed because of high resistance of poly-silicon. Although a metal lining structure is applied in order to lower the resistance, the FIT-CCD is used for a limited purpose such as a broadcasting system or the likes because of its difficulty in manufacturing and miniaturization. Moreover, the FIT-CCD consume higher power than a normal CCD due to higher driving speed.